Systolic Arrays (SA) provide efficient mechanisms for processing a variety of data, from image and video processing to neural networks. The scalar core provides the control and orchestration of the SA, and the L2 scratchpad provides the streaming memory interface to the SA to enable sustained high performance. To support different kinds of applications, MEEP proposes a common SA Shell template for all of them. This template fixes the interfaces with the scalar processor, and memory, but the final internal structure of the computational block will depend on the nature of the application to be executed.
Addressing target audiences and expressing needs
- Use of research Infrastructure
- Collaboration
- Fellowship to advance my/our research
we are looking for early adopters, uses cases, private and public companies/institutions in Risc-v business manufacturing
- Public or private funding institutions
- Research and Technology Organisations
- Academia/ Universities
R&D, Technology and Innovation aspects
Current: the SA Shell is integrated into the VAS tile.
Next: design special systolic accelerators for AI and video processing that will use the SA Shell and demonstrate the performance of the solution in various target technologies.