The MEEP VPU supports RISC-V vector instructions v0.7.1, and is equipped to work in two modes of operations: ACME-classic-mode, and ACME- mode. ACME-classic-mode is applicable when the operand vectors are short dense vectors. To exploit the available spatial and temporal localities in these scenarios, the vector loads and stores are carried out through the traditional cache hierarchy. The limit for operand vector length in this mode is determined by the vector register space on the VPU. The MEEP VPU operates in ACME-mode for operand vectors longer than this limit. The ACME-mode is also applicable for short, and long sparse vectors and is effective when the operand vectors do not achieve significant performance gains due to the normal cache hierarchy (i.e. streaming, non-unit stride or sparse memory accesses).
Addressing target audiences and expressing needs
- Use of research Infrastructure
- Collaboration
- Fellowship to advance my/our research
We are looking for early adopters, uses cases, private and public companies/institutions in Risc-v business manufacturing.
- Public or private funding institutions
- Research and Technology Organisations
- Academia/ Universities
R&D, Technology and Innovation aspects
Current stage: MEEP version of the VPU, with configurable pairs of lanes from 1 pair up to 8, and memory interface for data in the L2-scratchpad
Next stage: improving compatibility of MEEP.EPI according to the new development from EPI